The present invention relates to power semiconductor devices and in particular relates to insulated gate devices such as upright metal oxide semiconductor (UMOS) field effect transistors and insulated gate bipolar transistors (IGBTs). This application is related to copending application Ser. No. 08/797,535, filed concurrently herewith to James A. Cooper, Jr. for xe2x80x9cStructure For Increasing The Maximum Voltage Of Silicon Carbide Power Transistorsxe2x80x9d (hereinafter, xe2x80x9cthe Cooper applicationxe2x80x9d). The Cooper application is incorporated entirely herein by reference.
The present invention relates to power semiconductor devices and particularly power MOSFETs (metal-oxide-semiconductor field effect transistors) and IGBTs (insulated gate bipolar transistors). Power MOSFETs and IGBTs are small, reliable, electronically controllable switching devices that have growing application in high voltage/high power devices and integrated circuits. Power MOSFETs and IGBTs have a variety of applications in numerous fields including communications, consumer applications, data processing, military, industrial, automotive, and related markets. In particular, power MOSFETs have inherently higher switching speeds than bipolar transistors and are accordingly particularly useful in high-frequency applications.
The Cooper application referred to and incorporated by reference above describes novel UMOS and IGBT structures that takes greater advantage of the intrinsic properties of silicon carbide (SiC). As set forth in the Cooper application, the intrinsic properties of silicon carbide are such that it can theoretically handle a peak electric field eight times higher than can silicon, leading to the possibility that silicon carbide switching devices can be fabricated with drift regions eight times thinner than comparable silicon devices, with doping of the drift regions being about twelve times higher. Because the resistance of the drift region is proportional to the thickness and inversely proportional to the doping, the specific on resistance of a silicon carbide device can be from 100-200 times smaller than a comparable silicon device of equal voltage rating. This means that the silicon carbide device can be 100-200 times smaller than the comparable silicon device. Alternatively, if the silicon carbide device is formed with the same area as the comparable silicon device, the specific on-resistance of the silicon carbide device will be about 100-200 times lower than the silicon device.
As further set forth in the Cooper application, these theoretical advantages of silicon carbide have not yet been reached because the maximum voltage in silicon carbide MOSFETs is limited by the breakdown field of the silicon dioxide (SiO2) insulator rather than by the silicon carbide itself. Although the oxide may not actually fail until fields of about 107 volts per centimeter (V/cm) are reached, in reality the long term reliability of the oxide degrades severely above about 2-3xc3x97106 V/cm. Thus, the capability of the oxide is already less than the theoretical breakdown field of silicon carbide. Furthermore, the dielectric constants of silicon dioxide and silicon carbide exasperate the problem. In particular, their exists a 2.5:1 ratio between the dielectric constant of silicon dioxide and silicon carbide. Accordingly, Gauss"" law requires that the maximum field in the silicon carbide portion of a device be limited to around 1xc3x97106 V/cm to avoid reaching the breakdown limit in the oxide.
As a result of all of these factors, silicon carbide power transistors are practically limited to a blocking voltage much lower than that of which silicon carbide is theoretically capable.
The Cooper application addresses this problem by incorporating a protective layer beneath the bottom of the trench adjacent to the insulator (typically silicon dioxide). This protective region protects the field insulator in the trench from the degrading or breakdown effects of a large positive voltage applied to the drain. Thus, the additional p-type layer described in the Cooper application protects the oxide so that the device can make the maximum usage of silicon carbide""s high breakdown field. The Cooper application also sets forth the results of device simulation carried out using a commercially available simulation software package. The simulation confirms that the p-type layer protects the oxide in the intended manner.
This simulation also indicates, however, that the protection offered by the additional p-type layer at the bottom of the trench increases as the distance (xe2x80x9cdxe2x80x9d in FIGS. 1 and 2) along the trench wall between the p-type layer of the transistor and the p-type protection layer decreases. Stated in the alternative, the protective effect on the oxide is better when these two p-type portions of the Cooper device are closer to one another.
As a proviso noted in the Cooper application, however, decreasing this distance between the two p-type regions tends to encourage pinch-off between them which can eventually block all current at forward bias. Basic calculations indicate that for typically useful doping concentrations in the p and n-type portions of the UMOS e.g. (p=2xc3x971017 cmxe2x88x923, n=2.5xc3x971015 cmxe2x88x923), pinch off will occur when the distance between the two p-type portions is less than about 1.5 microns.
Obtaining a 1.5 micron gap, however, presents some problems. First, from a processing standpoint, physically defining such a distance requires that the trench be etched to a depth of about 3 microns. Accordingly, if aluminum is used in typical fashion as a reactive ion etching (RIE) mask, at least about 6750 xc3x85 of aluminum will be theoretically required. In reality, however, because of the thickness variation of aluminum deposition and etch rate variation during RIE, 8,000 xc3x85 of aluminum would be typically necessary for a safe mask. The aluminum mask then would need to be removed using lift off technology in order to keep straight sidewalls in the trench. Lifting off an 8,000 xc3x85 layer of aluminum is technically difficult, however, and is best avoided if at all possible.
Alternatively, if the two p-type layers are spaced 1.5 microns or more apart to minimize the processing problems, the greater distance will correspondingly minimize the protective effect for which the additional p+ layer is included in the structure.
Accordingly, there exists a need to tailor the geometry of the structures disclosed in the Cooper application to minimize the possibility of pinching off the current and to avoid technical difficulties in masking and etching deep trenches solely for the purpose of establishing a minimum distance between the p-type layers.
Therefore, it is an object of the present invention to provide an insulated gate structure that minimizes the possibility of pinching off the current while at the same time taking advantage of the full capabilities of UMOS and IGBT structures, particularly in silicon carbide.
The invention meets this object with an insulated gate transistor that exhibits increased power capacity, reduced on resistance, and prevents current pinch-off. In one aspect, the invention comprises a UMOS field-effect transistor, including a trench and a trench oxide on the walls and bottom of the trench. A protective region is beneath the bottom portion of the trench oxide of the transistor for protecting the trench oxide from the degrading or breakdown effects of a large voltage applied across the device. A current enhancing layer is between the protective region and the channel of the insulated gate structure, and the current enhancing layer is preferably more heavily doped than the remainder of the n-type drain region of the transistor.
The foregoing and other objects, advantages and features of the invention, and the manner in which the same are accomplished, will be more readily apparent upon consideration of the following detailed description of the invention taken in conjunction with the accompanying drawings, which illustrate preferred and exemplary embodiments, and wherein: